This invention relates to a high-speed low-noise output buffer, and more particularly, to an output buffer apparatus and method for controlling switching delay of the output buffer and change in current with respect to time during a switching operation so as to control the switching speed with maximum efficiency across process, temperature and supply voltage variations.
The most significant requirement of an output buffer is to drive the output voltage to the specified logic threshold by the time the voltage is needed and to maintain that level with adequate noise margins as long as required. As the noise generated during switching of an output buffer may vary according to process speed, temperature and supply voltage, a way of controlling the switching noise substantially independent of such variations is needed.
Conventional output buffers do not control the switching noise so as to be independent of variations in process or operating conditions. Typically, a switching speed is adopted at which the noise margins are maintained even if process or operating conditions vary. Generally, as system speeds increase, the operating speeds of the components also must increase. As a result, the switching time requirement shortens making it more difficult to maintain the noise margins under varying process and operating conditions. For example, process conditions vary from device to device, even though such devices may be rated the same (i.e., a processor rated for 30 MHz may run at 34.5 MHz for a fast chip and 30.0 MHz for a slow chip, while still satisfying 30 MHz rating within acceptable tolerances). A buffer designed to have adequate switching speed within noise margins for a fast case, may have an inadequate switching speed for a slow case.
One source of noise is the current spike caused by the charging or discharging of a load capacitor at the output line of the output buffer during switching. Such load capacitor sinks or sources current when charging or discharging, respectively, resulting in the current spike. Associated with the current spike is a change in current with respect to a change in time (di/dt) which causes a bounce in the power or ground voltage which is equal to L di/dt, where L is the effective inductance of the bond wires and the power or ground pins. This inductive noise lowers the noise margins for the system and is detrimental to the overall system noise immunity. For example, in a package of output buffers which share common power or ground pins, the switching of one or more of the buffers may create a spike at the ground pin which causes another non-switching driver to appear switched during the spike. Thus, the di/dt value needs to be limited to an acceptable level.
Limiting the di/dt of an output buffer, however, also limits the speed at which the output can switch. With an ideal di/dt waveform, as shown at curve A in FIG. 1 (i.e., a square wave), the fastest switching time possible for changing the voltage on the load capacitor, C.sub.L, by a voltage differential dV at a given di/dt is: EQU t=[(4C.sub.L dV)/(di/dt)].sup.1/2
where
t=delay time to charge or discharge C.sub.L PA1 C.sub.L =load capacitance PA1 dV=change in voltage at output
Accordingly, there is a trade-off between speed and di/dt. As described above, the conventional approach for designing output buffers is to design for a particular delay and di/dt at which speed and noise margin requirements both are met. For example, a conventional approach is to attempt to hold the switching delay and di/dt values constant for variations in process or operating conditions. As speed requirements increase and it becomes tougher to meet the noise margin requirements for varying process and operating conditions, designers have looked to the relation between t and di/dt to find alternative approaches for increasing speed while meeting noise margin requirements.
As can be seen from the formula above, approaches for decreasing switching delay time, t, include (1) reducing the load capacitance, C.sub.L, (2) reducing the change in voltage, dV and (3) increasing the di/dt.
With regard to decreasing the load capacitance, the ability to decrease such capacitance is limited by the capacitance of the board signal paths combined with the input capacitance of load devices receiving the output signal from the output buffer.
With regard to decreasing the change in voltage dV, the CMOS rail-to-rail voltage swing may be reduced to the TTL voltage level swing. Such decreasing is accomplished by reducing the voltage swing between the logic "0" state and the logic "1" state to the output, or by precharging the output to an intermediate level, then charging the output to the desired level.
The remaining approach for improving the delay, t, is by increasing the di/dt value. Increasing the di/dt increases speed (decreases delay), but also increases the noise. Accordingly, there is a need for increasing di/dt while assuring that noise margin requirements are met for both fast and slow cases as defined by varying process and operating conditions.
One approach which enables an increased di/dt without significantly increasing the noise is to use a better package in which the inductances of the bond wires and power and ground pins are reduced. Thus, an increase in di/dt can be offset to a certain extent by a decrease in inductance, L, for the noise equation, (noise=L di/dt).
As the output buffers come in packages and the switching of outputs simultaneously causes the resulting noise spike to increase by superposition, the di/dt also can be increased by reducing the number of outputs which switch simultaneously. For example, if ten buffers each having a di/dt of 30 mA/ns normally are switched simultaneously resulting in a di/dt of 300 mA/ns (i.e., 10.times.30 mA/ns), decreasing the number of buffers which switch simultaneously to five allows the di/dt of each buffer to be increased to up to 60 mA/ns to generate the same 300 mA/ns.
As the di/dt waveforms in practice do not achieve the ideal square wave shape, but more closely resemble the sine wave as shown at curve B of FIG. 1, another approach is to improve the di/dt curve so as to more closely resemble the ideal curve. Referring to the di/dt curve B of FIG. 1, which shows the curve as actually achieved, the first half of the sine wave is the lead portion and the last half of the sine wave is the lag portion. Known approaches addressing the di/dt curve shape have improved the shape of the lead portion only, and ignored the shape of the lag portion.
The control over the lead portion of the di/dt curve for an output buffer 10 traditionally has been implemented by limiting the slew rate on the gate input of the output drive transistor 11 using a predriver circuit 13 as shown in FIG. 2. The switching delay versus di/dt trade-off is complicated, however, in that delay variations occur of up to three or four to one for MOS transistors as a result of process, temperature, and power supply variations. For example, process and operating system variations may result in fastest case components having actual speeds of 45 MHz and slowest case speeds of 15 MHz for a specified 25 MHz processor. An output buffer which generates an acceptable amount of L di/dt noise and switches with a reasonable speed in the fastest case may be unacceptably slow in the slowest case.
One approach for adjusting the slew rate under various conditions is to transform the predriver of FIG. 2 from a simple inverter 13 to a current limited pull-up device by inserting an additional transistor controlled by an analog voltage. Referring to FIG. 3, a portion of such an output buffer 10' is shown. The signal to be output is fed into a predriver including NMOS and PMOS transistors 12, 14. The output signal then is pulled up by a PMOS transistor 16 under the control of an analog voltage to limit the slew on the gate input of the drive transistor 18. Accordingly, the di/dt is controlled. However, it is only the lead portion of the di/dt curve which is controlled. The lag portion is dependent on the width of the output transistor, which is held constant according to this approach. Thus, the lag portion is not controlled. Furthermore, such an approach is undesirable because of the need to distribute a sensitive analog voltage in the I/O frame--precisely the location where the maximum amount of noise is being generated.
Accordingly an output buffer in which the di/dt value is controlled over the lead and lag portions of the switching curve is not known. Further an output buffer in which the switching delay and di/dt value are controlled for variations in process and operating conditions is not known.